1. Field
Embodiments of the invention relate to electronic devices, and more particularly, in one or more embodiments, to junction field effect transistors for voltage protection for electronic devices.
2. Description of the Related Technology
Certain electronic circuits can be exposed to overvoltage or undervoltage conditions. The overvoltage or undervoltage conditions can include, for example, electro static discharge (ESD) events arising from the abrupt release of charge from an object or person to an electronic system. Such overvoltage or undervoltage conditions can damage electronic circuits or adversely affect the operations of the circuits. Various protection circuits have been developed to provide protection over electronic circuits from overvoltage or undervoltage conditions.
Referring to FIG. 1, a conventional system including an internal circuit and a voltage protection circuit for protecting the internal circuit will be described below. The illustrated system 100 includes an internal circuit such as an amplifier circuit 110, a voltage protection circuit 120, a first node N1, and a second node N2. The amplifier circuit 110 includes an input configured to receive an input voltage signal VIN via the first node N1, the voltage protection circuit 120, and the second node N2.
The voltage protection circuit 120 serves to conduct the input voltage signal VIN during normal operation in which the input voltage signal VIN is within a selected range, for example, between rail voltages. If an overvoltage or undervoltage condition (in which the input voltage signal VIN is outside the selected range) occurs, the voltage protection circuit 120 reduces the input voltage signal VIN or blocks it from passing to the amplifier circuit 110, thereby protecting the amplifier circuit 110.
Referring to FIG. 2A, one example of a conventional voltage protection circuit will be described below. The illustrated protection circuit 200 can be at least part of the voltage protection circuit 120 of FIG. 1. The protection circuit 200 can include a first junction field effect transistor (JFET) 210, a second junction field effect transistor (JFET) 220, a first diode D1, a second diode D2, and first to third nodes N1-N3.
The first JFET 210 includes a source S1 electrically coupled to the first node N1, a drain D1 electrically coupled to the second node N2, and a gate G1 electrically coupled to the third node N3. The first JFET 210 serves as a primary device for conducting an input voltage signal VIN therethrough during normal operation while limiting the input voltage signal VIN when an overvoltage or undervoltage condition occurs.
The second JFET 220 includes a source S2 electrically coupled to the third node N3, a drain D2 electrically coupled to the second node N2, and a gate G2 electrically coupled to the third node N3. The second JFET 220 serves to recycle a gate current from the gate G1 of the first JFET 210. It is desirable to decrease the size of the second JFET 220.
The first diode D1 includes an anode coupled to the second node N2, and a cathode coupled to a first voltage rail Vcc. The second diode D2 includes an anode coupled to a second voltage rail VEE, and a cathode coupled to the second node N2. The first and second diodes D1, D2 together serve as a clamping circuit.
It is common to look at device characteristics, for example, as shown in FIG. 2B, where the drain-source current IDS of a JFET is plotted as a function of the drain-source voltage VDS for various gate voltages Vg. As can be seen, for small VDS, the drain—source current IDS rises rapidly in what is known as the “triode” region, generally indicated 10, in which the JFET functions like a resistor. However, as VDS increases, the JFET enters into the “pinch off” region at a pinch-off voltage Vp, generally designated 20, in which the IDS versus VDS family of curves are nominally horizontal so that the current is largely controlled by the gate voltage (this region of operation is also known as the “linear” region or mode). As the drain-source voltage VDS increases still further, then breakdown processes cause the drain-source current IDS to rise more rapidly again in response to increasing drain-source voltage VDS.
Referring back to FIG. 2A, during normal operation, the first JFET 210 operates in the triode region, functioning like a resistor having a drain-source on resistance RDSON coupled between the first node N1 and the second node N2. As the drain-source on resistance RDSON increases, noise from the first JFET 210 also increases. Thus, it is desirable to reduce the drain-source on resistance RDSON by, for example, increasing the size of the first JFET 210.
In an undervoltage condition, in which the input voltage signal VIN is lower than the lower limit of the selected range, the first JFET 210 has both of its p-n junctions (source-gate and drain-gate junctions) reverse-biased, and operates like a resistor in the linear region 20 (see FIG. 2B). The second JFET 220 is reverse-biased with its gate-source voltage VGS equal to 0 V. The drain-source current IDSS of the second JFET 220 is smaller than the drain-source current IDSS of the first JFET 210, and is fed back to the second node N2, thereby recycling the gate current of the first JFET 210 to increase the current flowing through the second node N2.
In an overvoltage condition in which the input voltage signal VIN is higher than the upper limit of the selected range, the first JFET 210 operates as a PNP bipolar transistor (for a p-channel JFET). In an example in which the first JFET 210 is a p-channel JFET, a first p-n junction between the source S1 and the gate G1 is forward-biased, and a second p-n junction between the drain D1 and the gate G1 is reverse-biased, thereby generating a base current from the gate G1 that is beta times smaller than the collector current at D1 (where beta is a process-dependent current gain, from base to collector, of a bipolar transistor). The beta of JFET 210 operating as a bipolar transistor is poorly controlled, and can vary over a wide range of values, which in turn causes the overvoltage-current to vary similarly. To better control the overvoltage-current, the second JFET 220 is sized as small as the process rules allow, and acts to limit the base current coming from JFET 210. In this manner, the current flowing through JFET 210 in an overvoltage condition is limited by the maximum operating current of JFET 220 (IDSS).